fix logic

This commit is contained in:
Kevin Fenzi 2018-03-22 22:54:55 +00:00
parent 6dcc71fe94
commit 37dd6c16a4

View file

@ -11,7 +11,7 @@ image_type = raw
# bridge_name = virbr0 # bridge_name = virbr0
{% if ansible_architecture == 'ppc64' or ansible_architecture == 'ppc64le' %} {% if ansible_architecture == 'ppc64' or ansible_architecture == 'ppc64le' %}
cpus = 1 cpus = 1
{% elif %} {% else %}
cpus = 2 cpus = 2
{% endif %} {% endif %}
memory = 3096 memory = 3096